Requirements

• proficiency with HDL (Verilog/System Verilog and/or VHDL) design languages, simulation and synthesis tools,
• working knowledge of Clock Domain Crossing (CDC) and Static Timing Analysis (STA),
• experience with Code Development Process within the team, git-based source control,
• fluency in Russian, communicative English or Polish,
• background in the field of Image processing algorithms and Computer Vision will be an asset,
• experience with RTL advanced testing techniques will be an asset,
• knowledge of scripting languages (Python, Bash) will be an asset.

Responsibilities

• design and implement FPGA-based solutions using RTL (Verilog/System Verilog and/or VHDL),
• develop and optimize digital logic designs, integrating various IPs and interfaces to meet functional and performance requirements,
• debug and troubleshoot FPGA designs, addressing issues related to timing, functionality, and integration,
• develop and execute FPGA verification tests, including simulation and hardware testing to ensure design correctness and robustness,
• technical research tasks.

We offer

• competitive salary,
• social benefits,
• elastic form of employment,
• remote work with occasional visits in the office.